Basic device operation — raising 1,000 questions

1. The transistor as a gate-controlled barrier#

The slide draws a planar MOSFET: two heavily doped n⁺ regions (source S and drain D) on either side of a p-type channel, covered by a thin oxide and a metal gate. Electrons enter from the source, cross the channel and leave through the drain. Along the channel the conduction band forms a barrier: the n⁺ source and drain have their band edge near the Fermi level, the p region pushes it up. A positive gate voltage \(V_g\) pulls the barrier down (the colored curves, from red to blue), a drain voltage lowers the drain side. The electrons in the source (the colored circles) that are above the barrier top pass; the others are reflected.

The simplest model that keeps this physics is one-dimensional. The channel is a stretch of silicon, described by an effective mass \(m^* = 0.19\,m_0\) (the transverse mass of the Δ valleys whose light direction lies along the channel). Its band edge \(E_c(x)\) is given by hand: 10 nm of source at \(E_c = 0\), a channel of length \(L_g\) whose top sits at \(E_{top} = E_{top,0} - \alpha V_g\), and 10 nm of drain at \(E_c = -V_d\), joined by smooth steps 1 nm wide. \(\alpha \leq 1\) is the gate coupling, the fraction of the gate voltage that reaches the channel. The source Fermi level is \(\mu_S = 50\) meV above its band edge and the drain's is \(\mu_D = \mu_S - qV_d\). Electrons cross ballistically, with the transmission \(T(E)\) that open-nemo computes for this potential, and the current of the single transverse mode is the Landauer integral

No electrostatics is solved here: the barrier is imposed. Section 4 adds it.

The left panel is the band diagram of the slide, computed. On the right the current rises in a straight line on the log scale, by six orders of magnitude between \(V_g = 0\) and 0.4 V, then saturates once the barrier top drops below the source Fermi level: the threshold. The slope below threshold is 59.3 mV per decade; the dashed line is \(k_BT\ln 10/q = 59.5\) mV/dec. Above threshold the current, 3.7 µA at 0.5 V, approaches the ceiling of one ballistic mode, \((2q/h)\,k_BT\ln(1 + e^{\mu_S/k_BT}) = 4.1\) µA, reached when every source electron moving toward the drain is transmitted (the remaining 10 % are reflected by the smooth steps of the band edge).

2. Why 60 mV/dec: the Fermi tail#

The slide asks the questions behind this line: what is the density of states, what is the Fermi distribution, why 60 mV/dec? Below threshold the barrier top \(E_{top}\) is many \(k_BT\) above \(\mu_S\). Only the electrons in the tail of the Fermi function, \(f(E) = 1/(1 + e^{(E-\mu)/k_BT}) \approx e^{-(E-\mu)/k_BT}\), get over, and all of those that do pass. The current is therefore proportional to \(e^{-(E_{top}-\mu_S)/k_BT}\), and lowering the barrier by \(\alpha\,\Delta V_g\) multiplies it by \(e^{\alpha q\Delta V_g/k_BT}\). One decade needs

The swing is a property of the electrons' thermal distribution, not of the transistor: no amount of engineering of a thermionic barrier makes it steeper than \(k_BT\ln10/q\). The calculation checks both factors, the temperature and the gate coupling:

The swing scales with temperature, 15.3 mV/dec at 77 K and 79.3 at 400 K, and with \(1/\alpha\): a gate that controls only 80 % of the channel potential gives 74.7 mV/dec. In a real planar MOSFET \(\alpha < 1\) because the gate shares control with the depletion charge underneath (the oxide and depletion capacitances form a divider), and this is one reason the industry moved to fins and nanowires, where the gate surrounds the channel.

3. Confinement and tunneling: what a short channel does#

The next slide lists the questions that modern devices add: material choices, crystal structures, geometry, confinement and tunneling, strain. The tunneling question can be answered with the same model. When the channel is short, the barrier is thin near its top, and electrons below \(E_{top}\) tunnel through it. Their current does not follow the Fermi tail one-to-one with the barrier height, so the swing degrades.

Down to 10 nm the swing stays at the thermal limit. At 7 nm it rises to 62 mV/dec, at 5 nm to 86 mV/dec and at 3 nm to 143 mV/dec, and the off current at \(V_g = 0\) grows by more than three orders of magnitude. The energy-resolved current on the right shows why: for the 30 nm channel essentially everything flows above the barrier top, for the 4 nm channel 99.7 % of the current tunnels through it. This source-to-drain tunneling sets one of the limits of scaling, and it cannot be described by a band diagram and a Fermi function alone: it needs quantum mechanics, and — as Lecture 1.3 argues — the right band structure inside the barrier.

4. A three-dimensional device: a gate-all-around nanowire#

The model above imposes the barrier. In a real transistor the barrier is set by electrostatics: the gate, the doping and the electrons themselves, through Poisson's equation. open-nemo's GateAllAroundWire solves this self-consistently for a silicon nanowire wrapped by its gate: a 2 nm diameter [100] wire, 1 nm of oxide, an 8 nm gate and 8 nm source and drain extensions doped \(10^{20}\) cm⁻³, with the cross-section's subbands of two valley pairs (four each) carrying ballistic current along the wire (the mode-space approach of the gate-all-around nanowire FET notebook). Six gate voltages at \(V_d\) = 0.5 V take about half a minute.

The self-consistent wire reproduces the textbook picture. The lowest subband along the wire (left) is the band diagram of slide 4: a barrier under the gate that the gate voltage pulls down, with the drain side 0.5 V lower. The current (right) rises from about 2 pA to 5 µA, close to the curve in the slide's animation, with a swing of 62 mV/dec between 0 and 0.1 V: the gate wrapped around a 2 nm wire controls the channel almost perfectly (\(\alpha \approx 59.5/62.1 = 0.96\)). Above 0.3 V the channel fills with electrons, their charge screens the gate, and the current bends over. Note that in a flat potential the lowest subband of this 2 nm wire lies 0.42 eV above the bulk band edge (see the nanowire notebook): confinement is not a small correction here.

5. Beyond the transistor: optical interactions#

The last picture leaves the transistor. A thin GaAs layer between AlGaAs barriers confines electrons in the conduction band and holes in the valence band. An electron dropping from the first conduction-band level to the first valence-band level emits a photon of energy

where \(E_{e1}\) and \(E_{h1}\) are the confinement energies measured from the band edges. The questions the slide adds — the valence band, light emission and absorption, electron–electron and electron–phonon interactions — are all needed for lasers, LEDs and photodetectors.

The levels come from closed effective-mass boxes: the well between two 10 nm barriers, with the offsets of open-nemo's material registry for Al${0.3}$Ga${0.7}$As on GaAs, the electron masses of the two materials, and the heavy-hole mass along [001], \(m_{hh} = m_0/(\gamma_1 - 2\gamma_2)\) from the GaAs Luttinger parameters (used in both layers, a simplification).

A 20 nm well emits 13 meV above bulk GaAs (872 nm); an 8 nm well emits at 1.48 eV (840 nm), a 3 nm well at 1.60 eV (776 nm), close to the visible red. The emission color is set by the thickness of a layer, a few nanometres, through confinement. The infinite-well formula \(\hbar^2\pi^2/2m^*L^2\) in brackets overestimates the levels badly once the well is narrow, because the wave function leaks into the barriers; a real design also needs the valence-band mixing that a single heavy-hole mass ignores (the eight-band k·p heterostructures and quantum-well optics notebooks include it).

6. A thousand questions, and where this course answers them#

The slides end with the learning outcomes: explain the working principles of these devices, explain the physical processes in them, and relate their performance to materials and design criteria. The list of questions maps onto the course. The conduction and valence bands, effective masses, non-parabolicity and the crystal come with band structure (Lecture 1.3 and the tight-binding sections); doping, density of states and the Fermi distribution with the electrostatics of devices (Lecture 1.4); confinement and tunneling with the open-system and resonant-tunneling sections; geometry and strain with the nanowire and ultra-thin-body material; scattering by electrons and phonons with the transport sections and Lecture 2.

Summary#

• A one-dimensional barrier model with ballistic transmission reproduces the textbook band diagram and the \(\log I_d\)–\(V_g\) curve; a single mode saturates near \((2q/h)k_BT\ln(1+e^{\mu_S/k_BT})\) = 4.1 µA.
• Below threshold only the Fermi tail crosses the barrier, so the swing is \(S = (k_BT/q)\ln 10/\alpha\): 59.3 mV/dec computed against 59.5 at 300 K, 15.3 at 77 K, 74.7 for \(\alpha\) = 0.8.
• Channels shorter than about 7 nm let electrons tunnel under the barrier top: the swing rises to 86 mV/dec at 5 nm and 143 mV/dec at 3 nm.
• A self-consistent 2 nm gate-all-around silicon wire gives 62 mV/dec and a current from about 2 pA to 5 µA between 0 and 0.5 V.
• In a GaAs/Al${0.3}$Ga${0.7}$As quantum well the photon energy moves from 1.44 eV (20 nm) to 1.60 eV (3 nm) by confinement alone.

Exercises#

1. Repeat the swing calculation at 4 K. What limits the swing of the 30 nm channel there, and what would you have to change in the model to recover \(k_BT\ln10/q\)?
2. Replace the transverse mass \(0.19\,m_0\) by the longitudinal mass \(0.916\,m_0\) (the Δ valleys whose heavy direction lies along the channel). How does the swing of the 4 nm channel change, and why?
3. Make the gate coupling depend on the channel length, e.g. \(\alpha = 1 - e^{-L_g/2\lambda}\) with a natural length \(\lambda\) = 2 nm, and combine it with the tunneling of Section 3. Which effect dominates at 5 nm?
4. Find the well width at which the GaAs quantum well emits at 800 nm.

Further reading#

• Gate-all-around nanowire FET
• Gate geometry and scaling
• Wire tunnel FETs, which beat 60 mV/dec by filtering the Fermi tail with a band-to-band tunnel junction
• Quantum-well optics
• Lecture 1.3: band structure in nanoelectronics and Lecture 1.4: PN junction to device scaling
• R. F. Pierret, Semiconductor Device Fundamentals (Addison-Wesley, 1996).
• M. Lundstrom and J. Guo, Nanoscale Transistors: Device Physics, Modeling and Simulation (Springer, 2006).
• The animation on slide 7: en.wikipedia.org/wiki/File:Threshold_formation_nowatermark.gif